The embodiments described herein relate to a semiconductor device and, more particularly, to a semiconductor device having a convex type gate pattern and a method for manufacturing the same.
Recently, due to increased integration of a semiconductor device, the size of the gate is gradually scaled down and the length of the channel length between source and drain regions is shortened. Due to this, the switching performance is lowered and the power consumption is increased. Furthermore, it may create a punch-through phenomenon which causes device characteristics to deteriorate.
Among the issue points, the short channel effect due to reduction of the gate channel length is most serious.
As the semiconductor device becomes highly integrated, a nano device with higher speed and lower operation voltage (e.g., 1V through 2V) is required which then requires a lower threshold voltage. However, if the threshold voltage is lowered to far, it is impossible to control the device due to the short channel effect. Furthermore, the short channel effect causes a drain induced built in leakage (DIBL) due to hot carriers.
Research regarding the short channel effect have grown. However, the short channel effect still remains due to the continuing integration of devices.
In the prior semiconductor device and fabrication method thereof, it is difficult to achieve very high speed performance due to the short channel effect in the transistor. Changes to the effective channel length and ion implantation process have been made to improve the short channel effect, but the above problems still remain.